library verilog;
use verilog.vl_types.all;
entity lab5_vlg_sample_tst is
    port(
        clk             : in     vl_logic;
        key_row         : in     vl_logic_vector(3 downto 0);
        key_sel         : in     vl_logic_vector(1 downto 0);
        m               : in     vl_logic_vector(1 downto 0);
        ra              : in     vl_logic_vector(1 downto 0);
        rd              : in     vl_logic;
        rst             : in     vl_logic;
        wr              : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end lab5_vlg_sample_tst;
